Testing Electronic Design Automation (EDA) tools hinges on the availability of benchmarks—programs written in Hardware Description Languages (HDLs) like Verilog, SystemVerilog, and VHDL. While benchmark collections exist, their diversity remains limited. This limitation is increasingly problematic given the growing demand for training large language models in the EDA domain. In order to address this challenge, this paper introduces enhancements in the variety of programs produced by ChiGen, a tool for synthesizing realistic Verilog designs. Originally developed to test Cadence Design Systems’ Jasper\textsuperscript{TM} Formal Verification Platform, ChiGen has demonstrated its capability to uncover zero-day bugs in tools such as Verible, Verilator, and Yosys. This work expands ChiGen’s capabilities to include SystemVerilog constructs such as classes, interfaces, and packages, as well as formal verification primitives like assertions, sequences, and properties. These additions significantly increase both structural diversity and the semantic representativity of the generated programs.