Probabilistic Synthesis of Verilog Programs to Test EDA Tools
Rafael Fontes Sumitani
2024/1 - POC1
Orientador: Fernando Magno Quintão Pereira
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Electronic Design Automation (EDA) tools are software applications used by engineers in the design, development, simulation, and verification of electronic systems and integrated circuits. These tools typically process specifications written in a Hardware Description Language (HDL), such as Verilog, SystemVerilog or VHDL. Thus, effective testing of these tools requires programs written in these languages. This work presents ChiBench, a curated benchmark suite comprising more than 50K programs mined from open-source repositories. Additionally, this work also introduces ChiGen, a tool which synthesizes Verilog programs from scratch based on a probabilistic language model, thereby increasing the number of available inputs for testing.
2024/1 - POC1
Orientador: Fernando Magno Quintão Pereira
Link para vídeo
PDF Disponível